The present invention relates to a resistive ferroelectric memory cell including a selection transistor and a storage capacitor. The storage capacitor has one electrode at a fixed cell-plate voltage and another electrode connected to a first zone of the selection transistor having a first conduction type. The selection transistor and the storage capacitor are disposed in a semiconductor substrate of a second conduction type opposite to the first conduction type.
Ferroelectric storage configurations, in which the cell-plate voltage is set firmly to half the supply voltage (Vcc/2) of the storage configuration, are distinguished by fast storage operations. However, in the case of those storage configurations, a problem which occurs is that of a possible loss of data stored in the storage capacitors: since cell nodes at the storage capacitors are floating as long as the selection transistors are off, and those cell nodes form parasitic pn junctions in relation to the semiconductor substrate, leakage currents which necessarily occur through those pn junctions cause the cell-node voltage to fall to the ground voltage Vss. In that case other nodes of the ferroelectric storage capacitors remain at the fixed cell-plate voltage Vcc/2. As a result, the content of the ferroelectric storage capacitors can be destroyed by reprogramming.
In order to avoid that data loss, the memory cells are refreshed, in a similar way to that in the case of DRAMs, before their content is destroyed. Refreshing is carried out by bit lines of the storage configuration being precharged to half the supply voltage Vcc/2 and the cell nodes likewise being charged up to half the supply voltage Vcc/2 by activating the word lines, so that zero volts drop across the storage capacitors.
Refreshing in that way is complicated and requires additional operations, which should be avoided as far as possible.
It is accordingly an object of the invention to provide a resistive ferroelectric memory cell, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and which is configured in such a way that a leakage current at a cell node can no longer cause reprogramming of the memory cell, so that it is possible to dispense with refreshing the memory cell.
With the foregoing and other objects in view there is provided, in accordance with the invention, a resistive ferroelectric memory cell, comprising a selection transistor having first and second zones of a first conduction type. A storage capacitor has one electrode at a fixed cell-plate voltage and another electrode connected to the first zone of the selection transistor. A semiconductor substrate has a second conduction type opposite the first conduction type. The storage capacitor and the selection transistor are disposed in the semiconductor substrate. A resistor is disposed between the other electrode of the storage capacitor and the fixed cell-plate voltage. The resistor has a resistance R2 such that R3 less than  less than R2 less than  less than R1, in which R1 is a reverse resistance of a pn junction between the first zone of the selection transistor and the semiconductor substrate and R3 is a resistance between the first zone and the second zone of the selection transistor, in a turned-on state.
In this way a resistive connection between the floating cell node and the outer node of the storage capacitor is produced in the memory cell according to the invention, so that the leakage current of the parasitic pn junction is compensated for and approximately the cell-plate voltage (Vcc/2) is present at both electrodes of the storage capacitor. Therefore, unintentional reprogramming of the storage capacitor can no longer take place. It should further be noted that the resistance of the blocked, switched-off selection transistor can still be present in parallel in this case. However, as a rule this resistance is very small.
In the memory cell according to the invention, it is essential that:
(a) the resistance of the resistor is significantly lower than the reverse resistance of the pn junction; and
(b) the floating cell node is pulled up to the cell-plate voltage in a shorter time than the refresh time which is otherwise needed.
In the resistive ferroelectric memory cell according to the invention, it is firstly ensured that the reading and writing operation is virtually undisturbed by the resistance. It is secondly ensured that the leakage current of the parasitic pn junction is compensated for by the resistor, and approximately the cell-plate voltage is present on both sides of the ferroelectric storage capacitor. Therefore, unintentional reprogramming of the storage capacitor can no longer take place.
In accordance with another feature of the invention, the first zone of the selection transistor is preferably the drain zone, but if appropriate can also be the source zone.
In accordance with a further feature of the invention, the resistor is provided as a thick oxide transistor between the first zone of the selection transistor and a highly doped zone of the first conduction type in the semiconductor substrate.
In accordance with an added feature of the invention, the resistor is provided by a weakly doped region of the first conduction type between the first zone of the selection transistor and a highly doped zone of the first conduction type in the semiconductor substrate.
In accordance with an additional feature of the invention, in both of the above-described optional embodiments for the resistor, the highly doped zone of the first conduction type is connected to the one electrode of the storage capacitor through a contact plug, for example made of doped polycrystalline silicon or aluminum.
In accordance with yet a concomitant feature of the invention, the resistor is formed directly between the one electrode and the other electrode of the storage capacitor. In this case, the resistor can be a high-resistance polycrystalline resistor.
In the resistive memory cell according to the invention, it is particularly advantageous that unintended reprogramming of its memory content as a result of a leakage current through the parasitic pn junction between the first zone and the region surrounding the latter, that is to say, for example, the semiconductor substrate, is excluded. In addition, it is readily possible to use a normal word-line decoder. Nor is the capacity of the word lines enlarged. Finally, even when the supply voltage is switched off, no unintentional reprogramming of the storage content of the memory cell will take place.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a resistive ferroelectric memory cell, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.